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integrated circuit systems, inc. 874005ag www.icst.com/products/hiperclocks.html rev. a january 25, 2006 1 ICS874005 pci e xpress ? j itter a ttenuator g eneral d escription the ICS874005 is a high performance diff- erential-to-lvds jitter attenuator designed for use in pci express systems. in some pci express systems, such as those found in desktop pcs, the pci express clocks are generated from a low bandwidth, high phase noise pll frequency synthesizer. in these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the pll synthesizer and from the system board. the ICS874005 has 3 pll bandwidth modes: 200khz, 400khz, and 800khz. the 200khz mode will provide maximum jitter attenuation, but with higher pll tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. the 400khz provides an intermediate bandwidth that can easily track triangular spread profiles, while providing good jitter attenuation. the 800khz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter attenuation will not be as good as the lower bandwidth modes. because some 2.5gb serdes have x20 multipliers while others have than x25 multipliers, the 874005 can be set for 1:1 mode or 5/4 multiplication mode (i.e. 100mhz input/125mhz output) using the f_sel pins. the ICS874005 uses ics 3 rd generation femtoclock tm pll technology to achive the lowest possible phase noise. the device is packaged in a 24 lead tssop package, making it ideal for use in space constrained applications such as pci express add-in cards. f eatures ? five differential lvds output pairs ? one differential clock input ? clk and nclk supports the following input types: lvpecl, lvds, lvhstl, sstl, hcsl ? output frequency range: 98mhz - 160mhz ? input frequency range: 98mhz - 128mhz ? vco range: 490mhz - 640mhz ? cycle-to-cycle jitter: 30ps (maximum) ? 3.3v operating supply ? 3 bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs ? 0c to 70c ambient operating temperature ? available in both standard and lead-free rohs compliant packages hiperclocks? ic s qa0 nqa0 b lock d iagram bw_sel 0 = pll bandwidth: ~200khz float = pll bandwidth: ~400khz (default) 1 = pll bandwidth: ~800khz pll b andwidth f_sela 0 5 (default) 1 4 f_selb 0 5 (default) 1 4 vco 490 - 640mhz phase detector m = 5 (fixed) pulldown oea f_sela bw_sel clk nclk f_selb mr oeb pullup qa1 nqa1 qb0 nqb0 qb1 nqb1 pulldown pulldown pullup pulldown float p in a ssignment ICS874005 24-lead tssop 4.40mm x 7.8mm x 0.92mm package body g package top view nqb2 nqa1 qa1 v ddo qa0 nqa0 mr bw_sel v dda f_sela v dd oea 1 2 3 4 5 6 7 8 9 10 11 12 qb2 v ddo qb1 nqb1 qb0 nqb0 f_selb oeb gnd gnd nclk clk 24 23 22 21 20 19 18 17 16 15 14 13 pulldown qb2 nqb2 0 = ~200khz float = ~400khz 1 = ~800khz
integrated circuit systems, inc. 874005ag www.icst.com/products/hiperclocks.html rev. a january 25, 2006 2 ICS874005 pci e xpress ? j itter a ttenuator t able 1. p in d escriptions t able 2. p in c haracteristics t able 3a. o utput e nable f unction t able t able 3b. pll b andwidth /pll b ypass c ontrol s t u p n is t u p t u o b e o / a e ox a q n / x a qx b q n / x b q 0z i hz i h 1d e l b a n ed e l b a n e r e b m u ne m a ne p y tn o i t p i r c s e d 4 2 , 12 b q , 2 b q nt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 3 , 21 a q , 1 a q nt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 3 2 , 4v o d d r e w o p. s n i p y l p p u s t u p t u o 6 , 50 a q n , 0 a qt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 6t u o _ b f nt u p t u o. t u p t u o k c a b d e e f l a i t n e r e f f i d g n i t r e v n i 7r mt u p n in w o d l l u p e r a s r e d i v i d l a n r e t n i e h t , h g i h c i g o l n e h w . t e s e r r e t s a m h g i h e v i t c a s t u p t u o d e t r e v n i e h t d n a w o l o g o t ) x q n ( s t u p t u o e u r t e h t g n i s u a c t e s e r s t u p t u o e h t d n a s r e d i v i d l a n r e t n i e h t , w o l c i g o l n e h w . h g i h o g o t ) x q ( . s l e v e l e c a f r e t n i l t t v l / s o m c v l . d e l b a n e e r a 8l e s _ w bt u p n i / p u l l u p n w o d l l u p . b 3 e l b a t e e s . t u p n i h t d i w d n a b l l p 9v a d d r e w o p. n i p y l p p u s g o l a n a 0 1a l e s _ ft u p n in w o d l l u p . s t u p t u o x a q n / x a q r o f n i p t c e l e s y c n e u q e r f . s l e v e l e c a f r e t n i l t t v l / s o m c v l 1 1v d d r e w o p. n i p y l p p u s e r o c 2 1a e ot u p n ip u l l u p e r a s t u p t u o x a q n / x a q e h t , h g i h n e h w . s n i p a q r o f n i p e l b a n e t u p t u o e c n a d e p m i h g i h a n i e r a s t u p t u o x a q n / x a q e h t , w o l n e h w . e v i t c a . s l e v e l e c a f r e t n i l t t v l / s o m c v l . e t a t s 3 1k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 4 1k l c nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 6 1 , 5 1d n gr e w o p. d n u o r g y l p p u s r e w o p 7 1b e ot u p n ip u l l u p e r a s t u p t u o x b q n / x b q e h t , h g i h n e h w . s n i p b q r o f n i p e l b a n e t u p t u o e c n a d e p m i h g i h a n i e r a s t u p t u o x b q n / x b q e h t , w o l n e h w . e v i t c a . s l e v e l e c a f r e t n i l t t v l / s o m c v l . e t a t s 8 1b l e s _ ft u p n in w o d l l u p . s t u p t u o x b q n / x b q r o f n i p t c e l e s y c n e u q e r f . s l e v e l e c a f r e t n i l t t v l / s o m c v l 0 2 , 9 10 b q , 0 b q nt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d 2 2 , 1 21 b q , 1 b q nt u p t u o. s l e v e l e c a f r e t n i s d v l . r i a p t u p t u o l a i t n e r e f f i d : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k s t u p n i l l p h t d i w d n a b w b _ l l p 0z h k 0 0 2 ~ 1z h k 0 0 8 ~ t a o l fz h k 0 0 4 ~
integrated circuit systems, inc. 874005ag www.icst.com/products/hiperclocks.html rev. a january 25, 2006 3 ICS874005 pci e xpress ? j itter a ttenuator t able 4b. lvcmos/lvttl dc c haracteristics , v dd = v dda = v ddo = 3.3v5%, t a = 0c to 70c a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5 v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ja 70c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. t able 4a. p ower s upply dc c haracteristics , v dd = v dda = v ddo = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a d d e g a t l o v y l p p u s g o l a n a 5 3 1 . 33 . 35 6 4 . 3v v o d d e g a t l o v y l p p u s t u p t u o 5 3 1 . 33 . 35 6 4 . 3v i d d t n e r r u c y l p p u s r e w o p 5 8a m i a d d t n e r r u c y l p p u s g o l a n a 5 1a m i o d d t n e r r u c y l p p u s t u p t u o 5 1 1a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i e g a t l o v h g i h t u p n i , r m , b e o , a e o b l e s _ f , a l e s _ f 2v d d 3 . 0 +v l e s _ w bv d d 4 . 0 -v v l i e g a t l o v w o l t u p n i , r m , b e o , a e o b l e s _ f , a l e s _ f 3 . 0 -8 . 0v l e s _ w b 4 . 0v v m i e g a t l o v d i m t u p n il e s _ w bv d d 1 . 0 - 2 /v d d 1 . 0 + 2 /v i h i t n e r r u c h g i h t u p n i b e o , a e ov d d v = n i v 5 6 4 . 3 =5a b l e s _ f , a l e s _ f l e s _ w b , r m v d d v = n i v 5 6 4 . 3 =0 5 1a i l i t u p n it n e r r u c w o l , l e s _ w b b e o , a e o v d d v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a , r m b l e s _ f , a l e s _ f v d d v , v 5 6 4 . 3 = n i v 0 =5 -a
integrated circuit systems, inc. 874005ag www.icst.com/products/hiperclocks.html rev. a january 25, 2006 4 ICS874005 pci e xpress ? j itter a ttenuator t able 4d. lvds dc c haracteristics , v dd = v dda = v ddo = 3.3v5%, t a = 0c to 70c t able 5. ac c haracteristics , v dd = v dda = v ddo = 3.3v5%, t a = 0c to 70c t able 4c. d ifferential dc c haracteristics , v dd = v dda = v ddo = 3.3v5%, t a = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i k l cv d d v = n i v 5 6 4 . 3 =0 5 1a k l c nv d d v = n i v 5 6 4 . 3 =5 i l i t n e r r u c w o l t u p n i k l cv d d v = n i v 5 6 4 . 3 =0 5 1a k l c nv d d v = n i v 5 6 4 . 3 =0 5 1 - v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c 2 , 1 e t o n ; e g a t l o v t u p n i e d o m n o m m o c 5 . 0 + d n gv d d 5 8 . 0 -v v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 1 e t o n h i . v s i k l c n , k l c r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 2 e t o n d d . v 3 . 0 + l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d o e g a t l o v t u p t u o l a i t n e r e f f i d 5 7 25 7 35 8 4v m v d o v d o e g n a h c e d u t i n g a m 0 5v m v s o e g a t l o v t e s f f o 2 . 15 3 . 15 . 1v v s o v s o e g n a h c e d u t i n g a m 0 5v m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o8 90 6 1z h m t ) c c ( t i j1 e t o n , r e t t i j e l c y c - o t - e l c y c 5 10 3s p t ) o ( k s3 , 2 e t o n ; w e k s t u p t u o 0 9s p t r t / f e m i t l l a f / e s i r t u p t u o% 0 8 o t % 0 20 0 30 5 5s p c d oe l c y c y t u d t u p t u o8 42 5% . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 1 e t o n . s n o i t i d n o c d a o l l a u q e h t i w d n a e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 2 e t o n v t a d e r u s a e m o d d . 2 / . n o i t c u d o r p n i d e t s e t t o n . n o i t a z i r e t c a r a h c y b d e e t n a r a u g e r a s r e t e m a r a p e s e h t : 3 e t o n
integrated circuit systems, inc. 874005ag www.icst.com/products/hiperclocks.html rev. a january 25, 2006 5 ICS874005 pci e xpress ? j itter a ttenuator p arameter m easurement i nformation c ycle - to -c ycle j itter d ifferential i nput l evel 3.3v lvds o utput l oad ac t est c ircuit o utput s kew v cmr cross points v pp gnd clk nclk v dd clock outputs 20% 80% 80% 20% t r t f v swing d ifferential o utput v oltage s etup t pw t period t pw t period odc = x 100% ? ? ? ? qa0, qa1 qb0:qb2 nqa0, nqa1 nqb0:nqb2 t jit(cc) = t cycle n ? t cycle n+1 1000 cycles t cycle n t cycle n+1 scope qx nqx lv d s 3.3v5% power supply +? float gnd v dd, v ddo v dda o utput d uty c ycle /p ulse w idth /p eriod o utput r ise /f all t ime ? ? ? 100 out out lv d s dc input v od / v od v dd out out lvds dc input ? ? ? v os / v os v dd o ffset v oltage s etup t sk(o) nqy qy nqx qx qa0, qa1 qb0:qb2 nqa0, nqa1 nqb0:nqb2
integrated circuit systems, inc. 874005ag www.icst.com/products/hiperclocks.html rev. a january 25, 2006 6 ICS874005 pci e xpress ? j itter a ttenuator a pplication i nformation figure 2 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v dd /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 2. s ingle e nded s ignal d riving d ifferential i nput w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v dd = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. v_ref r1 1k c1 0.1u r2 1k single ended clock input clk nclk vdd p ower s upply f iltering t echniques as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ICS874005 provides sepa- rate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd , v dda , and v ddo should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 1 illustrates how a 10 resistor along with a 10 f and a .01 f bypass capacitor should be connected to each v cca pin. f igure 1. p ower s upply f iltering 10 v dda 10 f .01 f 3.3v .01 f v dd
integrated circuit systems, inc. 874005ag www.icst.com/products/hiperclocks.html rev. a january 25, 2006 7 ICS874005 pci e xpress ? j itter a ttenuator f igure 3c. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 3b. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 3d. h i p er c lock s clk/ n clk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 3a to 3d show inter- face examples for the hiperclocks clk/nclk input driven by the most common driver types. the input interfaces suggested f igure 3a. h i p er c lock s clk/ n clk i nput d riven by ics h i p er c lock s lvhstl d river here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example in figure 3a, the input termination applies for ics hiperclocks lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v i nputs : lvcmos c ontrol p ins : all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. a 1k resistor can be used. r ecommendations for u nused i nput and o utput p ins o utputs : lvds all unused lvds output pairs can be either left floating or terminated with 100 across. if they are left floating, we recommend that there is no trace attached.
integrated circuit systems, inc. 874005ag www.icst.com/products/hiperclocks.html rev. a january 25, 2006 8 ICS874005 pci e xpress ? j itter a ttenuator s chematic e xample figure 5 shows an example of ICS874005 application sche- matic. in this example, the device is operated at v dd =3.3v. the r3 100 r1 10 c8 .1uf r2 100 + - + - f_selb bw_sel clk c7 .1uf f_sela mr c6 .1uf c3 10uf c4 0.01u oea (u1:4) u1 874005_tssop24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 nqb2 nqa1 qa1 vddo qa0 nqao mr bw_sel vdda f_sela vdd oea clk nclk gnd gnd oeb f_selb nqb0 qb0 nqb1 qb1 vddo qb2 r5 50 vddo = 3.3v zo = 50 ohm oeb zo = 50 ohm zo = 50 ohm (u1:23) zo = 50 ohm zo = 50 ohm c5 10uf nclk r6 50 lvpecl driv er r4 50 (u1:11) zo = 50 ohm vdd = 3.3v decoupling capacitor should be located as close as possible to the power pin. the input is driven by a 3.3v lvpecl driver. f igure 5. ICS874005 s chematic e xample lvds d river t ermination a general lvds interface is shown in figure 4. in a 100 differential transmission line environment, lvds drivers require a matched load termination of 100 across near 100 ohm differiential transmission line r1 100 3.3v + - lvds_driv er 3.3v f igure 4. t ypical lvds d river t ermination the receiver input. for a multiple lvds outputs buffer, if only partial outputs are used, it is recommended to terminate the un-used outputs.
integrated circuit systems, inc. 874005ag www.icst.com/products/hiperclocks.html rev. a january 25, 2006 9 ICS874005 pci e xpress ? j itter a ttenuator p ower c onsiderations this section provides information on power dissipation and junction temperature for the ICS874005. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ICS874005 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 5% = 3.465v, which gives worst case results. ? power (core) max = v dd_max * (i dd_max + i dda_max ) = 3.465v * (85ma + 15ma) = 346.5mw ? power (outputs) max = v ddo_max * i ddo_max = 3.465v * 115ma = 398.48mw total power _max = 346.5mw + 398.48mw = 745mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for hiperclocks tm devices is 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature q ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 63c/w per table 6 below. therefore, tj for an ambient temperature of 70c with all outputs switching is: 70c + 0.745w * 63c/w = 117c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). t able 6. t hermal r esistance ja for 24-l ead tssop, f orced c onvection ja by velocity (linear feet per minute) 0 200 500 multi-layer pcb, jedec standard test boards 70c/w 63c/w 60c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
integrated circuit systems, inc. 874005ag www.icst.com/products/hiperclocks.html rev. a january 25, 2006 10 ICS874005 pci e xpress ? j itter a ttenuator r eliability i nformation t ransistor c ount the transistor count for ICS874005 is: 1206 t able 7. ja vs . a ir f low t able for 24 l ead tssop ja by velocity (linear feet per minute) 0 200 500 multi-layer pcb, jedec standard test boards 70c/w 63c/w 60c/w
integrated circuit systems, inc. 874005ag www.icst.com/products/hiperclocks.html rev. a january 25, 2006 11 ICS874005 pci e xpress ? j itter a ttenuator p ackage o utline - g s uffix for 24 l ead tssop t able 8. p ackage d imensions reference document: jedec publication 95, mo-153 l o b m y s s r e t e m i l l i m m u m i n i mm u m i x a m n4 2 a- -0 2 . 1 1 a5 0 . 05 1 . 0 2 a0 8 . 05 0 . 1 b9 1 . 00 3 . 0 c9 0 . 00 2 . 0 d0 7 . 70 9 . 7 ec i s a b 0 4 . 6 1 e0 3 . 40 5 . 4 ec i s a b 5 6 . 0 l5 4 . 05 7 . 0 0 8 a a a- -0 1 . 0
integrated circuit systems, inc. 874005ag www.icst.com/products/hiperclocks.html rev. a january 25, 2006 12 ICS874005 pci e xpress ? j itter a ttenuator t able 9. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated circuit systems, incorpor ated (ics) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patent s, or licenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability or other extr aordinary environmental requirements are not recommended without additional processing by ics. ics reserves the right to change any circuitry or specifications without noti ce. ics does not authorize or warrant any ics product for use in life support devices or critical medical instruments. the aforementioned trademarks, hiperclocks and femtoclock are trademarks of integrated circuit systems, inc. or its subsidiarie s in the united states and/or other countries. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t g a 5 0 0 4 7 8 s c ig a 5 0 0 4 7 8 s c ip o s s t d a e l 4 2e b u tc 0 7 o t c 0 t g a 5 0 0 4 7 8 s c ig a 5 0 0 4 7 8 s c ip o s s t d a e l 4 2l e e r & e p a t 0 0 5 2c 0 7 o t c 0 f l g a 5 0 0 4 7 8 s c id b tp o s s t " e e r f - d a e l " d a e l 4 2e b u tc 0 7 o t c 0 t f l g a 5 0 0 4 7 8 s c id b tp o s s t " e e r f - d a e l " d a e l 4 2l e e r & e p a t 0 0 5 2c 0 7 o t c 0 . t n i a l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s " f l " n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n

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